1. Field of the Invention
The present invention relates generally to systems, methodologies and techniques for improving design for manufacturability of integrated circuits and semiconductors, and more particularly relates to systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations.
2. Description of the Related Art
Traditionally, semiconductor design for even modestly complex semiconductors has involved the use of a series of masks, layered one on top of the other, to represent the completed design, where each mask represents a processing step. The impact of even small errors in the design of a single mask can propagate to the complete failure of an entire design. It has therefore become important that the design of individual masks be optimized against such errors even before fabrication of the semiconductor begins.
To avoid such costly errors, a typical semiconductor manufacturer implements a fairly complex set of layout analyses and transformations (or modifications) to improve the yield of their designs and minimize the design errors of individual masks. Today's integrated circuits can typically contain eight or more metal layers and two poly layers, which translates into several dozen mask layers. A modern design with 50 million transistors can contain more than a billion shapes. GDSII layout files can reach sizes in excess of 100 Gigabytes (GB) after traditional optical proximity correction features are added and the geometry is flattened. The computational load of performing analyses and transformations on modern IC layouts keeps growing.
Additionally, as diffraction-limited optical systems have become implemented in semiconductor manufacturing, what is printed on the wafer may not be what was designed on the mask. One such error is typically referred to as an optical proximity effect. One technique that has been developed for identifying optical proximity effects that will require a transformation of the layout is optical proximity correction, or OPC. OPC is typically either rule-based or model-based. Rule-based OPC involves automatically altering a feature depending on a list of predetermined rules, and generally uses a geometric algorithm to find a particular feature type. This feature is then automatically changed, based on the rule. Model-based OPC uses a fast simulation technique to predict how a mask feature will appear on the wafer (i.e., based on the simulated, optical characterizations of the manufacturing equipment). Iterative modifications are made until an acceptable error exists between the designer's intent and the simulated wafer feature.
The OPC problem is significant for its complexity. Most algorithms become easier to perform each year as CPU speed is constantly increasing. However, OPC involves using today's processors to design tomorrow's processors, which means that the problem complexity scales with the speed to today's processors. In fact, the OPC complexity may scale more quickly than the current CPU speeds are increasing because of additional factors such as an increasing number of mask (i.e., metal) layers. Since the OPC problem involves storing a dynamic polygon database, tens or hundreds of GBs of memory are likely needed for good performance. These figures roughly double with each technology generation.
Thus, what is needed are systems and techniques that allow broader, yet efficient, means to perform computationally intensive transformations and analyses, such as OPC, on IC layouts as semiconductor feature size decreases and mask designs become more numerous and complex.